The present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved multi-stage charge pump, one or more cascaded stages of which incorporate respective drive signal recovery circuits, that enable the charge pump to operate over a larger voltage range and/or be referenced to a very small input voltage.
Electrical power for integrated circuits are typically supplied by one or more direct current (DC) power sources. In a number of applications the circuit may require one or more operating voltages that are different from the available supply voltage (which may be relatively low e.g., on the order of three volts or less). For example, memory devices such FLASH EEPROMs typically require a relatively high voltage to perform read and write operations. Another example is the increased complexity of video boards used in present day computers, which typically require that multiple power supplies operating at differing voltages be available on a single card. Because it is often not feasible to install additional power sources, many circuit designs incorporate charge pump circuits to generate higher local-use supply voltages.
A typical charge pump stage contains one or more pumping capacitors that are selectively charged and discharged through a series of selectively controlled switches to boost the supply voltage and thereby provide a higher output voltage. The number of charge pump stages may be increased or cascaded to correspondingly the multiply the supply voltage to high output values. An example of such a charge pump circuit is disclosed in the U.S. Pat. to Imi, No. 5,635,776 entitled xe2x80x9cCharge Pump Voltage Converter.xe2x80x9d
While a charge pump architecture of the type described in the Imi patent can provide a significant voltage boost, its use may not be feasible in applications where very little supply current is available, due to the fact that too much supply current is consumed during the generation of the switch control signals. Similarly, other prior art charge pump circuits that use multiple oscillators or other clock sources to provide the switch control signals may not be adequate where low current consumption is desirable, such as in portable, battery-powered devices.
Advantageously, this low current consumption issue is successfully addressed by the charge pump architecture disclosed in the U.S. Pat. to W. Shearon et al, No. 6,249,446 B1 (hereinafter referred to as the ""446 patent), entitled: xe2x80x9cCascadable, High Efficiency Charge Pump Circuit and Related Methods,xe2x80x9d issued Jun. 19, 2001, assigned to the assignee of the present application and the disclosure of which is incorporated herein.
The general architecture of a times-two (X2) voltage multiplier charge pump circuit according to the invention disclosed in the ""446 patent is diagrammatically illustrated at 10 in FIG. 1. This charge pump is a two-phase charge pump in that first and second charge-pumping capacitors 11 and 12 perform the same function but operate out of phase with one another. This redundancy serves to improve the efficiency of the charge pump. The first charge-pumping capacitor 11 is connected to a first set of switches 13, 14, 15, 16, while the second charge-pumping capacitor 12 is connected to a second set of switches 17, 18, 19, 20.
The switches 13-20 are driven by first and second sets of switch control signals ("PHgr"1-"PHgr"4 and "PHgr"1a-"PHgr"4a, respectively) having non-overlapping phases, generated by a controller 23. Switches 14, 18, 16, 20 may comprise PFETs and switches 13, 17, 15, 19 may comprise NFETS, for example. In this case, the control logic polarity for switches 14, 18, 16, 20 is opposite that of switches 13, 17, 15, 19. As shown by the switching signal waveforms adjacent to the "PHgr"1, "PHgr"2, "PHgr"3 and "PHgr"4 outputs of a clock generator 29 of a controller 23, the on-state control signals for the switches do not overlap, so as to prevent switches 13 and 14 from being turned on at the same time. Likewise, the switch pairs 17, 18, 15, 16 and 19, 20 are controlled so as to not be on at the same time, so as to avoid diminishing the operating efficiency of the charge pump.
In addition to clock generator 29, controller 23 includes a transient clamp network 24 (which may be configured as shown in FIG. 2) having outputs which provide the second set of switch control signals "PHgr"1a-"PHgr"4a. A first level-shifting capacitor 25 is connected between the "PHgr"1 output of the clock generator 29 and the "PHgr"1a output of the transient clamp network. Similarly, a second level-shifting capacitor 26 is connected between the "PHgr"2 and "PHgr"2a outputs, a third level-shifting capacitor 27 is connected between the "PHgr"3 and ("PHgr"3a outputs, and a fourth level-shifting capacitor 28 is connected between the "PHgr"4 and "PHgr"4a outputs.
The level-shifting capacitors 25, 26, 27, 28 cooperate with the transient clamp network 24, so that the second set of phase control signals is level-shifted relative to the first set of phase control signals. That is, the four switch control signals "PHgr"1-"PHgr"4 are coupled through the level-shifting capacitors 25, 26, 27, 28 to the transient clamp network. The transient clamp network 24 provides proper DC biasing, or auto-zeroing, on the non-driven side of the level-shifting capacitors.
As shown in FIG. 2, the transient clamp network 24 may include a set of four clamping, MOS transistors 31, 32, 33, 34. Transistor 31 is connected at its source to VOUT, its drain to "PHgr"1a, and its gate to "PHgr"3a. Transistor 32 is connected at its source to VOUT, its drain to "PHgr"3a, and its gate to "PHgr"1a. Transistor 33 is connected at its drain "PHgr"2a, its source to Vdd and its gate to "PHgr"4a. Transistor 34 is connected at its drain to "PHgr"4a, its source to Vdd and its gate to "PHgr"2a. 
The charge pump circuit 10 derives its power from a supply voltage Vdd at the input-supply side of the level-shifting capacitors 25, 26, 27, 28, and therefore uses nearly none of the developed output power. The four switch control signals "PHgr"1-"PHgr"4 and their level-shifted counterparts "PHgr"1a-"PHgr"4a control the switches 13-20, such that the two charge-pumping capacitors 11, 12 are alternatingly charged and discharged, to provide a multiplied output voltage VOUT.
As pointed out above, the first set of switch control signals includes a first pair of non-overlapping, switch control signals "PHgr"1, "PHgr"2 having opposite relative phases, and a second pair of switch control signals "PHgr"3, "PHgr"4, that do not overlap the first pair. The switch control signals "PHgr"3, "PHgr"4 also have phases opposite to one another. Because there is no overlap of the switch control signals between "PHgr"1, "PHgr"2 and "PHgr"3, "PHgr"4, and nearly no explicit current usage on the non-driven side of the level-shifting capacitors 25, 26, 27, 28, the charge pump circuit 10 operates with very high voltage conversion efficiency and power conversion efficiency, making it more efficient than conventional charge pump circuits under the same conditions.
As further described in the ""466 patent, the basic (X2 ) charge pump architecture of FIG. 1 may be expanded in a cascaded-stage fashion to provide higher orders of voltage multiplication of the supply voltage Vdd to X3 , X4 , . . . XN. FIG. 3 of the ""466 patent shows a non-limiting example of providing an additional charge pump stage (containing an additional pair of charge pump capacitors and associated chargexe2x80x94discharge switches) to realize X3 voltage multiplication. Now, although the same current conservation functionality of the architecture of FIG. 1 is realized for such higher order implementations, the present inventor has discovered a potential latch-up problem associated with the operation of the higher level voltage stages (e.g., X3 and above), particularly for low supply voltage applications.
In particular, it has been observed that where the supply voltage (Vdd) is very low (e.g., on the order of two to three volts or lessxe2x80x94a not uncommon situation for portable device applications), a respective higher order stage of the charge pump can xe2x80x98wake-upxe2x80x99 or be provoked into a state where one of the clamp rails of its transient clamp network is unable to be sufficiently biased to its appropriate operating voltage level. As a result, the clamp rail of this stage becomes xe2x80x98stuckxe2x80x99 substantially below the Xi output voltage provided by the immediately preceding lower order stage (for example, the iXP2 drive to the PFET transistor for the polarities of the circuit components of the charge pump of FIG. 1). At low voltage and high impedance, the charge pump is unable to develop sufficient gate-source voltage bias (Vgs) on the faulty device""s complement to pull it up to the required voltage level.
In accordance with the present invention, this problem is effectively obviated by augmenting at least upper level stages of the charge pump with respective drive signal recovery circuits. The drive signal recovery circuit of the present invention is operative to controllably clamp the affected level-shifted drive signal at a voltage sufficiently close to output voltage of the next lower (in cascaded voltage multiplication order) charge pump stage as to prevent the clamp rail from xe2x80x98hanging upxe2x80x99 at a reduced voltage. By reduced voltage is meant a voltage that would otherwise be too low for that stage of the charge pump to develop sufficient gate-source voltage bias (Vgs) on the faulty device""s complement to pull it up to the required voltage level.
As will be described, the switch control signal recovery circuit of the invention has an input terminal coupled to receive the output voltage of the immediately lower order charge pump stage, and an output terminal coupled to receive a first polarity, level-shifted switch control signal at one of the second outputs of the transient clamp network. Operation of the switch control signal recovery circuit is controlled by the second (complementary) polarity level-shifted switch control signal at another of the second outputs of the transient clamp network.
In a non-limiting, preferred embodiment, for the case of a positive polarity voltage, the switch control signal recovery circuit may comprise an auxiliary NFET switch (of opposite polarity to the clamped PFET), and having its (source-drain) current flow path series-coupled with a diode (such as a Schottky diode) between the input and output terminals of the recovery circuit. The gate of the auxiliary NFET switch is coupled to receive the complementary polarity level-shifted switch control signal during the off time of the clamped PFET.
When the auxiliary NFET switch is turned on by the complementary polarity level-shifted (NFET) switch control signal, it bias-clamps the level-shifted switch control rail at an augmented clamping voltage that effectively differs from the output voltage of the lower order charge pump stage by only the voltage drop across the Schottky diode. Because this augmented clamping voltage is very close to the output voltage of the next lower charge pump stage, it effectively ensures that sufficient gate-source voltage bias (Vgs) will be applied to the affected PFET switch to pull the level-shifted switching signal rail up to the required voltage level. As a consequence, a multi-stage charge pump incorporating the switch control signal recovery circuit of the invention is able to operate over a larger voltage range and/or be referenced to a very small input voltage.